A digital delay locked loop DLL apparatus and a method for correcting a duty cycle are disclosed, which correct the duty cycle used in a semiconductor or a computer system which needs a clock generator for compensating a skew between an external clock and internal clock.
A delay locked loop (DLL) is a circuit widely used for synchronizing an internal clock and an external clock in a synchronous memory of a semiconductor memory system. In the synchronous RAM, all operations such as write or read are supposed to be operated at a rising edge. However, certain elements of the semiconductor device cause a timing delay. For synchronizing operation timing at the rising edge in the synchronous RAM, the time delay must be eliminated. The DLL circuit receives the external clock signal and generates the internal clock signal for synchronizing two signals in order to eliminate the timing delay.
Various techniques have been used for controlling a clock signal of the DLL circuit.
At first, Donnelly et al. disclose xe2x80x9cAt frequency phase shifting circuit for use in a Quadrature clock generatorxe2x80x9d in U.S. Pat. No. 5,808,498 issued on Sep. 15, 1998 (hereinafter xe2x80x9cDonnellyxe2x80x9d). Donnelly teaches a phase shifting circuit including: a first differential amplifier having: a pair of field effect transistors configured to from a source coupled pair having a common node, and including a pair of inputs for receiving an input reference signal and complement thereof and a pair of output nodes; first and second current sources coupled respectively between the output nodes and a first supply rail, the first and second current sources sourcing a current value of I amperes: and a third current source coupled between the common node and a second supply rail, the third current source sinking a current value of 2I amperes; a filter circuit coupled across the output nodes, the filter circuit causing the output nodes of the differential amplifier to produce a pair of complementary triangle wave signals in response to the input reference signal and complement thereof; and a comparator having a pair of inputs coupled to receive the pair of complementary triangle wave signals, the comparator generating an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
Secondly, Japanese patent application (laid open) No. 2001-6399 discloses a semiconductor apparatus including: a phase controller for controlling phase of an external clock and generating an internal clock; a detector for detecting a frequency of the external clock that deviates from a phase control range of the phase frequency; a first operation mode and a second operation mode, which are switched by a control signal inputted from the outside; and an output circuit for outputting a signal without considering a result of the detector in the first operation mode and being became an output state in the second operation mode according to the result of the detector.
Finally, Japanese patent application (laid open) No. 11-353878 teaches a semiconductor apparatus having a clock phase control circuit for generating a second clock, which is delayed as much as a certain phase according to an external clock by controlling a received first clock phase and outputting data synchronized with one of a first clock and second clock, including: a clock frequency analyzer for analyzing a frequency of the first clock by responding to a signal representing an amount of delay of the first clock and outputting a control signal; and a clock selector for selecting a clock between the first clock and the second clock by responding to the control signal.
The above-mentioned conventional DLLs used in the DDR memory control a delay of whole phase based on a standard signal and compensated signal, however, the conventional DLLs cannot correct a phase delay caused by a duty error when data of external clock signal is processing, wherein the duty error is difference between real duty cycle and 50% duty cycle and it may be occurred during processing the external clock.
A DLL apparatus and a method for correcting a duty error are disclosed which utilize a blend circuit and generate an internal clock having 50% of a duty cycle.
A disclosed digital DLL apparatus for correcting a duty cycle comprises: a buffer for orderly outputting a first internal clock signal which is activated at an edge of clock by receiving an external clock signal; a delay line unit for receiving the first internal clock signal from the buffer, a first detection signal and a second detection signal and outputting a first delayed internal clock signal and second delayed internal clock signal by delaying the first internal clock signal as much as a predetermined delay amount according to the first and second detection signals; a blend circuit for bypassing the first delayed internal clock signal during the second delayed internal clocks signal is not activated and blending the first delayed internal clock signal and the second delayed internal clock signal in order to produce a blended clock signal when the second delayed internal clock signal is activated, wherein the blended clock signal has a phase of a falling edge mediated between falling edges of the first and second delayed internal clock signals; a delay model unit for estimating a delay amount generated during the blended clock signal travels to a data input/output pin (DQ pin) and outputting a compensated clock signal by compensating the blended clock signal based on the estimated delay amount; a direct phase detector for receiving the external clock signal, generating a first detection signal by comparing the external clock signal and the first compensated clock signal and outputting the first detection signal to the delay line unit; and a phase detector for receiving the first delayed internal clock signal and the second delayed internal clocks signal and generating a second detection signal by detecting phases of the first and second delayed internal clock signals.
A disclosed method for correcting a duty cycle comprises: a) determining whether rising edges of an external clock signal and a compensate clock signal are identically matched; b) activating a second delayed internal clock signal when the rising edges are identically matched; c) determining whether rising edges of the first delayed internal clock signal and second delayed internal clock signal are identically matched; and d) generating a blended clock signal having 50% duty cycle by blending phases of the first delayed internal clock signal and second delayed internal clock signal in case that rising edges of the first clock signal and second clock signal are matched identically.